1. Technical Field
Embodiments generally relate to a semiconductor apparatus, and more particularly, in one or more embodiments, to a duty cycle detection circuit and a semiconductor apparatus including the same.
2. Related Art
A synchronous semiconductor apparatus may be synchronized with a system bus. To put it another way, a synchronous semiconductor apparatus has a synchronous interface maintaining a fixed timing relationship between the synchronous semiconductor apparatus and another apparatus in the system, which is supposed to receive data outputted from the synchronous semiconductor apparatus, so that the data-receiving device can capture the data. A synchronous semiconductor apparatus uses a clock signal which is distributed throughout the system. Clock skew, however, occurs because the clock signal must be distributed using many transmission lines and transistors. Modern synchronous-communication systems with high data transmission rates may use delay-locked loop (“DLL”) circuits or phase-locked loop (“PLL”) to minimize data transmission errors due to clock skew.
Also, a semiconductor apparatus may include a duty cycle detection circuit for detecting the duty of a clock signal.
The duty cycle detection circuit may detect the duty cycle of the clock signal, that is, the ratio of a rising period and a falling period.